module hdmi_show_pic (
    input               IN_CLK_50M,
    input   [7:1]       PB,

    output              HDMI_CLK,
    output              HDMI_HS,
    output              HDMI_VS,
    output              HDMI_EN,
    output  [23:0]      HDMI_D,

    inout               IIC_SDA,
    inout               IIC_SCL
);
    
//====================================
//pll
wire    sys_clk_50m,vga_clk;
wire    locked,sys_rst_n;

pll pll_inst
(
    .clk_out1(sys_clk_50m),     // output clk_out1
    .clk_out2(vga_clk),         // 148.5MHz
    .reset(1'b0),               // input reset
    .locked(locked),            // output locked
    .clk_in1(IN_CLK_50M)        // input clk_in1
);
  
assign   sys_rst_n = locked;

//=====================================
//key
wire    center_flag;
wire    up_flag;
wire    down_flag;
wire    left_flag;
wire    right_flag;

key_filter#(
    .DVI_CNT(148)
)
key_filter_inst(
    .clk(vga_clk),			//50m
    .rst_n(sys_rst_n),
    .pb(PB),
    .center_flag(center_flag),
    .up_flag(up_flag),
    .down_flag(down_flag),
    .left_flag(left_flag),
    .right_flag(right_flag)
    );
//=================================
//vga_driver
wire		h_sync;
wire		v_sync;
wire		hv_de;

vga_driver#(
    .h_sync_pola(1),
    .v_sync_pola(1)
)
vga_driver_inst(
    .vga_clk(vga_clk),
    .rst_n(sys_rst_n),
    
    .h_sync(h_sync),
    .v_sync(v_sync),
    .hv_de(hv_de)
);
//=================================      
//rom   
wire  [16:0]  rd_rom_addr;
wire  [23:0]  rd_rom_data;
pic_rom pic_rom_inst (
  .clka(vga_clk),    // input wire clka
  .addra(rd_rom_addr),  // input wire [16 : 0] addra
  .douta(rd_rom_data)  // output wire [23 : 0] douta
);   

//=================================
// i2c
iic_cfg iic_cfg_inst(
    .clk(sys_clk_50m),            //50m
    .rst_n(sys_rst_n),
   
    .iic_sda(IIC_SDA),
    .iic_scl(IIC_SCL)
    );  
//================================
vga_show#(
	.h_pix(1920),
	.v_pix(1080)
)
vga_show_inst(

	.vga_clk(vga_clk),
	.rst_n(sys_rst_n),
	
	.h_sync(h_sync),
	.v_sync(v_sync),
	.hv_de(hv_de),
	
	.center_flag(center_flag),
	.up_flag(up_flag),
	.down_flag(down_flag),
	.left_flag(left_flag),
	.right_flag(right_flag),   
	
	.rd_rom_data(rd_rom_data),
	.rd_rom_addr(rd_rom_addr),
	
	.hdmi_hs(HDMI_HS),
	.hdmi_vs(HDMI_VS),
	.hdmi_en(HDMI_EN),
	.hdmi_d(HDMI_D)
);

assign	HDMI_CLK = vga_clk;  
    
endmodule
